The present invention relates to a circuit capable of generating, starting from a control current, another current that is n times larger than the control current.
When designing electronic circuits there is often the need of implementing current mirrors having a large ratio between the mirrored or output current and a reference or control current. Normally a current mirror is said to have a large ratio when it is in the order of ten. An additional requisite of current mirrors is to be very precise.
A classical circuit of a current mirror is shown in FIG. 1. When a particularly high precision is required, a modified circuit as the one depicted in FIG. 2 is often used. Such a modified circuit provides for a certain recovery of the base current by utilizing a third transistor, N3, for reducing an intrinsic error of the circuit. This error arises because in the control branch of the current mirror circuit comprising the diode-configured N1 transistor, among the current contributions there will be one due to the base currents of the two transistors of the mirror. This "offset " current produces an error proportional to the mirror ratio plus a term given by 1/.beta.. The additional transistor N3 permits a substantial recovery of the base currents of the transistors N1 and N2 and therefore a reduction of such an intrinsic asymmetry. This solution is not very effective in the case of circuits that must implement a relatively high mirror ratio, because the error remains large.
An operational transconductance amplifier (OTA), provided with a feedback loop including a transistor P, as depicted in FIG. 3, is often used in these cases. This circuit is capable of ensuring a high precision, even in the case of relatively large mirror ratios.
On the other hand, in certain applications, for example in telephone circuits (and, more generally, wherever signal transmission lines are also used as power supply lines), i.e. where it is particularly important that the circuits possess a high Power-Supply-Rejection-Ratio (PSRR), the known current mirrors have an impedance, as measured between the supply nodes, which is not sufficiently high to make their behavior relatively insensitive to the presence of AC signals on the supply line. Such a drawback of the known circuits becomes more marked in current mirrors having a relatively high mirror ratio. Moreover, in some applications, the precision of a circuit made according to the known techniques, e.g. as depicted in FIG. 3, is yet insufficient because of the finite gain of the OTA.
Note that the circuit of FIG. 3 has a somewhat different basic principle of operation from that of FIGS. 1 and 2: a feedback is employed for equalizing the voltage drops across the resistors R1 and R2. Since the reference current I.sub.rif is drawn across R1, and the mirrored current I.sub.spec across R2, the following relationship holds: EQU I.sub.spec =I.sub.rif R1/R2.
An easily implementable current mirror circuit has now been devised, which is capable of ensuring a high degree of precision also in relatively large mirror ratio circuits and has a high impedance as measured across the supply nodes.
Basically, the current mirror circuit provided by the present invention employs a field effect transistor for handling the current through a control terminal, e.g. a base terminal of a current output transistor, thus ensuring a high degree of precision of the current mirror. A frequency compensation of the gain stage is implemented by a feedback capacitance. The impedance of the circuit as measured across the supply nodes (PSRR) is increased by employing an additional transistor, functionally connected in the output branch of the current mirror circuit so as to form (together with the output branch transistor of the basic current mirror circuit), a cascode-type circuit capable of increasing the output impedance of the current mirror.
The output impedance of a current mirror circuit represents a most critical factor in determining a high impedance as measured across the supply nodes of the circuit, in view of the fact that it should be divided by the mirror ratio. The high loop gain provided by the use of a gain stage in the present invention not only reduces the error (thus increasing the precision of the circuit), but also helps to attain a high impedance across the supply nodes of the current mirror circuit. In fact, because the control current of the current output transistor is driven by the field effect transistor of the gain stage, it is possible to reduce the current levels in the two branches of the current mirror without negatively affecting performance. Such a current level reduction, beside producing a sensible saving in power consumption and facilitating sizing of the components of the current mirror, further increases the impedance. The output impedance of the circuit, i.e. the output impedance of the transistor that is driven by the field effect transistor of the gain stage, increases. This represents a further advantage per se, because the output transistor of the current mirror often must drive relatively high currents and therefore should have a relatively low output impedance.
The presently preferred embodiment provides a current mirror in which, like the circuit of FIG. 3, the mirror ratio is determined by the ratio of two resistors. However, the circuits of the present invention have some significant differences from those of FIG. 3. Not only is the complex OTA stage eliminated, but there are also some other notable differences. First, an additional amplifier stage is added to drive the output transistor. Second, this additional amplifier stage is preferably a field-effect transistor, and the output transistor is preferably bipolar. Third, an asymmetric configuration of bipolar transistors is used to drive the input of the additional amplifier stage. (In the presently preferred embodiment, an additional cascode transistor is interposed in only one of the two legs.) Fourth, a distinctive compensation capacitance configuration is used, as detailed below.
This has been advantageously implemented using a BiCMOS circuit, of which one sample implementation is shown in FIG. 4. The additional MOS amplifying stage performs two beneficial functions:
It increases the output impedance of the output transistor, which, if designed for carrying a relatively high output current, would have an intrinsically low output impedance. PA1 A second function of the MOS amplifying stage is to increase the loop gain of the circuit and to "decouple " the bipolar output transistor from the additional biplar cascode transistor (which would otherwise tend to depress the gain of the output transistor).
The additional transistor (P5 in the example of FIG. 4) serves the functions of) cascoding P2, thus increasing its output impedance and b) of allowing a "peculiar " compensation by means of the capacitance Cc that is not, as customarily done, connected to the gate of M4 but to the emitter of P5. This has been found to significantly improve the PSRR further.